This invention relates generally to ferroelectric memory cells. More particularly, the present invention relates to a method of operating a ferroelectric memory cell and related apparatus for improving retention performance, i.e. the ability of the memory cell to retain data when exercised over time.
In FIG. 1, a two-transistor two capacitor ("2T-2C") ferroelectric memory cell 10 is shown. Ferroelectric memory cell 10 includes two MOS transistors 12 and 14 respectively coupled to two ferroelectric capacitors 16 and 18. The data state of memory cell 10 is determined by the opposite polarization states of ferroelectric capacitors 16 and 18, as is explained in further detail below. A "one" data state may be represented by an "up" polarization state in ferroelectric capacitor 16 and a "down" polarization state in ferroelectric capacitor 18, whereas a "zero" data state may be represented by a "down" polarization state in ferroelectric capacitor 16 and an "up" polarization state in ferroelectric capacitor 18. The correlation between memory cell data states and the polarization of the ferroelectric capacitors in the memory cell is arbitrary and may be changed. Capacitors 16 and 18 must have opposite polarization directions for a valid data state, however.
The gate electrodes of access transistors 12 and 14 are coupled to a word line 20, which is also coupled to other ferroelectric memory cells (not shown in FIG. 1) in a row of an array of such cells. Word line 20 selectively energizes access transistors 12 and 14 to couple ferroelectric capacitors 16 and 18 to a differential bit line consisting of a bit line 24 and an inverted bit line 26. Bit line 24 and inverted bit line 26 are also coupled to other ferroelectric memory cells (not shown in FIG. 1) in a column of an array of such cells. Bit line 24 and bit line 26 receive the charge developed by poling (voltage pulsing) ferroelectric capacitors 16 and 18, which is later developed into a full logic voltage differential signal, usually five volts and ground. Ferroelectric capacitors 16 and 18 are also coupled to an active plate line 22, which is also coupled to other ferroelectric memory cells (also not shown in FIG. 1) in a row of an array of such cells.
The operation of a ferroelectric capacitor such as ferroelectric capacitor 16 or 18 in memory cell 10 is illustrated in FIGS. 2A-D by way of a series of hysteresis loop diagrams 28A-D and corresponding voltage waveform diagrams 38A-D. Hysteresis loop diagrams 28A-D show the electrical performance of a ferroelectric capacitor, wherein the x-axis represents the voltage applied across the capacitor, and the y-axis represents the charged evolved by the ferroelectric capacitor in response to the applied voltage. Corresponding waveform diagrams 38A-D are a series of two positive voltage pulses and two negative voltage pulses that are applied across a ferroelectric capacitor in a known sequence that illustrates the complete electrical behavior of a ferroelectric capacitor.
Hysteresis loop diagram 28A of FIG. 2A includes a hysteresis loop 30 and an initial operating point 32. Operating point 32 represents a ferroelectric capacitor having, by convention, an "up" polarization state, but with no applied voltage across the capacitor. The initial operating point 32 is achieved by a previous application and removal of a negative applied voltage across the capacitor. The operating point of the ferroelectric capacitor moves from operating point 32 to operating point 34 upon the application of a positive voltage pulse. Operating point 34 represents a fully saturated ferroelectric capacitor operating condition, i.e. further increases in applied voltage do not yield an appreciable amount of extra charge. The amount of charge evolved from operating point 32 to operating point 34 (the difference in the y-axis values) is designated "P". The "P" charge is termed a "switched charge" because the application of the external voltage pulse switches the polarization state of the ferroelectric capacitor. The leading edge of the first positive pulse in waveform diagram 38A is also labeled "P". Once the positive "P" pulse is removed, the operating point moves along hysteresis loop 30 from operating point to 34 to operating point 36. The amount of charge evolved from operating point 34 to operating point 36 is designated "Pa" (for "P"-after). The "Pa" charge is termed a "linear charge" because the removal of the external voltage pulse does not switch the polarization state of the ferroelectric capacitor, and the charge evolved by the capacitor is approximately linearly related to the applied voltage.
Hysteresis loop diagram 28B of FIG. 2B includes a hysteresis loop 30 and an initial operating point 36. Operating point 36 represents a ferroelectric capacitor having, by convention, a "down" polarization state, but with no applied voltage across the capacitor. The operating point of the ferroelectric capacitor moves from operating point 36 to operating point 34 upon the application of a second positive voltage pulse. The amount of charge evolved from operating point 36 to operating point 34 is designated "U", and it is a linear charge. The leading edge of the second positive pulse in waveform diagram 38B is also labeled "U". Once the positive "U" pulse is removed, the operating point moves along hysteresis loop 30 from operating point to 34 back to operating point 36. The amount of charge evolved from operating point 34 to operating point 36 is designated "Ua" (for "U"-after) and is approximately equal to the "U" and "Pa" charge components.
Hysteresis loop diagram 28C of FIG. 2C includes a hysteresis loop 30 and an initial operating point 36. The operating point of the ferroelectric capacitor moves from operating point 36 to operating point 40 upon the application of a first negative voltage pulse. The amount of charge evolved from operating point 36 to operating point 40 is designated "N", and it is a switched charge. The leading edge of the first negative pulse in waveform diagram 38C is also labeled "N". Once the negative "N" pulse is removed, the operating point moves along hysteresis loop 30 from operating point to 40 back to the initial operating point 32. The amount of charge evolved from operating point 40 to the initial operating point 32 is designated "Na" (for "N"-after).
Hysteresis loop diagram 28D of FIG. 2D includes a hysteresis loop 30 and an initial operating point 32. The operating point of the ferroelectric capacitor moves from operating point 32 to operating point 40 upon the application of a second negative voltage pulse. The amount of charge evolved from operating point 32 to operating point 40 is designated "D", and it is a linear charge. The leading edge of the second negative pulse in waveform diagram 38D is also labeled "D". Once the negative "D" pulse is removed, the operating point moves along hysteresis loop 30 from operating point to 40 back to operating point 32. The amount of charge evolved from operating point 40 to operating point 32 is designated "Da" (for "D"-after) and is approximately equal to the "D" and "Na" charge components.
Referring again to FIG. 2E, a ferroelectric material or capacitor is said to be "fully saturated" at operating points 34 and 40 of the hysteresis loop 30. The corresponding externally applied voltage at the saturation points is defined as "Vsat", for saturation voltage. Applying an external voltage beyond the saturation voltage results in extensions of the hysteresis loop 33A and 33B in which fewer and fewer ferroelectric "domains" switch in response to the applied voltage. A "partially saturated" ferroelectric material or capacitor is shown as a "sub-loop" 35 generated in response to an externally applied voltage less than saturation voltage. Another way of discerning the distinction between full saturation and partial saturation is that a partially saturated ferroelectric material will fall on a sub-loop, while a fully saturated ferroelectric material will fall on a fully expanded hysteresis loop, such as hysteresis loop 30 shown in FIG. 2E. A typical ferroelectric dielectric material used for ferroelectric capacitors is lead zirconate titanate ("PZT"). If the PZT material is used, the saturation voltage, Vsat, is about five volts. For full saturation, an externally applied voltage pulse of about six to seven volts is used. This will ensure that virtually all of the ferroelectric domains in the material have switched, with operating points along sections 33A and 33B of hysteresis loop 30. For partial saturation, which is operation on a sub-loop with voltages less than the saturation voltage, a voltage pulse of about four volts is used. A four volt pulse ensures that, while the ferroelectric material is not completely saturated, a sufficient quantity of charge is evolved that can be detected by conventional memory sense circuitry.
Referring now to FIG. 3, a waveform diagram shows the word line (WL), plate line (PL) and combined bit/inverted bit line (BIT and BIT) waveforms associated with the reading and restore operation of the 2T-2C ferroelectric memory cell 10 of FIG. 1. At time t1, all three signals are at a logic zero or ground potential. At time t2, the WL signal is energized to a logic one potential, usually five volts. With the WL signal at logic one, the gate electrodes of access transistors 12 and 14 are energized, but there is no current flow through the transistors because the PL, Bit, and/Bit signals are at a logic zero. At time t3 the PL signal is energized and charge is released onto the bit and inverted bit lines 24 and 26. The charge components are shown in the bit line waveform as levels 44 and 46, which correspond to charge components P and U. At time t4 the PL pulse is removed, and the bit line charge is modified. The P charge component 44 is modified by the subtraction of the Pa charge component, leaving a charge equal to (P-Pa) shown in the bit line waveform as level 45. The U charge component 46 is also modified by the subtraction of the Ua charge component, leaving a very small charge shown in the bit line waveform as level 47. Once the charge levels 45 and 47 have been established, they are sensed in the conventional manner and converted into full logic levels (dashed line between times t4 and t5). At time t5 the full logic levels have been established. In FIG. 3, the bit line is shown to be a logic one level, usually five volts, and the inverted bit line is shown to be at a logic zero level, usually at ground potential. At time t6, the PL signal is again pulsed to a logic one to restore the original data state in ferroelectric memory cell 10. At time 17, the PL signal is returned to a logic zero state, and at time t8, the WL signal is returned to a logic zero state. Ferroelectric memory cell 10 is now returned to the same quiescent state that existed at time t1, and is ready for another read and restore cycle. The reading/sensing/restoring operation demonstrated with respect to FIG. 3 is known in the prior art as the "up-down" sensing method, since the plate line must be transitioned up and back down before the bit line charge is sensed and converted into full logic levels.
The same word line and plate line signals shown in FIG. 3 can be used for a writing operation. The only difference is that prior to the sensing operation, bit lines 24 and 26 are written to, i.e. forced to receive a data state that may be the same or opposite to levels 45 and 47 shown in FIG. 3. The new bit line charge levels are again conventionally resolved into full logic levels, and with the exact WL and PL waveforms shown in FIG. 3.
Whether memory cell 10 is being read and restored, or written to, it is important to note that in the prior art that the first and second plate line pulses are the same voltage magnitude, about five volts. The first pulse is used to read the data state of memory cell 10 and has a pulsed voltage of about five volts. The second plate line pulse is used either restore the originally read data state, or to write a new data state to memory cell 10. In either case, in the prior art, the second pulse also has a pulsed voltage of about five volts.
The reading, restoring, and writing operations described above with respect to FIGS. 1-3 adequately exercise ferroelectric memory cell 10 such that it operates as a non-volatile memory cell. However, when operated for a long period of time, memory cell 10 eventually loses its ability to retain data. Various mechanisms such as compensation from mobile ions within the ferroelectric dielectric material in ferroelectric capacitors 16 and 18 are thought to be at least partially responsible for the lack of data retention.
What is desired is another method of operating memory cell 10 so that data retention performance can be extended beyond that which is possible with the current prior art technique described above.